DocumentCode :
258548
Title :
High-throughput hash-based online traffic classification engines on FPGA
Author :
Gandhi, Vaibhav R. ; Qu, Yun R. ; Prasanna, Viktor K.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Gandhinagar, Gandhinagar, India
fYear :
2014
fDate :
8-10 Dec. 2014
Firstpage :
1
Lastpage :
6
Abstract :
Traffic classification is used to perform important network management tasks such as flow prioritization and traffic shaping/pricing. Machine learning techniques such as the C4.5 algorithm can be used to perform traffic classification with very high levels of accuracy; however, realizing high-performance online traffic classification engine is still challenging. In this paper, we propose a high-throughput architecture for online traffic classification on FPGA. We convert the C4.5 decision-tree into multiple hash tables. We construct a pipelined architecture consisting of multiple processing elements; each hash table is searched in a processing element independently. The throughput is further increased by using multiple pipelines in parallel. To evaluate the performance of our architecture, we implement it on a state-of-the-art FPGA. Post-place-and-route results show that, for a typical 128-leaf decision-tree used for online traffic classification, our classification engine sustains a throughput of 1654 Million Classifications Per Second (MCPS). Our architecture sustains high throughput even if the number of leaves in the decision-tree is scaled up to 1K. Compared to existing online traffic classification engines on various platforms, we achieve at least 3.5× speedup with respect to throughput.
Keywords :
Internet; computer network management; data structures; decision trees; field programmable gate arrays; learning (artificial intelligence); parallel architectures; pattern classification; telecommunication computing; telecommunication traffic; C4.5 decision-tree; FPGA; Internet traffic classification; hash tables; hash-based online traffic classification engines; high-throughput architecture; machine learning; multiple processing elements; network management; pipelined architecture; Engines; Field programmable gate arrays; Indexes; Pipelines; Random access memory; Throughput; Vectors; FPGA; hash tables; traffic classification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4799-5943-3
Type :
conf
DOI :
10.1109/ReConFig.2014.7032530
Filename :
7032530
Link To Document :
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