Design and deployment of a generic ECC-based fault tolerance mechanism for embedded HW cores

Current practices for the design and deployment of hardware redundancy techniques in embedded systems remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging problems of engineering fault tolerance mechanisms in a generic way and providing suitable tools for coping with their deployment. This approach relies on metaprogramming to specify fault tolerance mechanisms and open compilers to automatically deploy such mechanisms on the selected hardware core. Our previous research has already shown the suitability of this approach for the generic design and automatic deployment of NMR strategies. In this paper, we explore the usefulness of the idea in the context of information redundancy. The main contribution is the development of a metaprogram for the provision of ECC-based fault tolerance in data storage elements (registers and memory modules). It is also shown to what extend such metaprogram can be useful for improving the reliability of communications between HW cores in embedded systems.