PAMS: Pattern Aware Memory System for embedded systems

Author

Hussain, Tassadaq ; Sonmez, Nehir ; Palomar, Oscar ; Unsal, Osman ; Cristal, Adrian ; Ayguade, Eduard ; Valero, Mateo ; Gursal, S.A.

Author_Institution

Comput. Sci., Barcelona Supercomput. Center, Barcelona, Spain

fYear

2014

fDate

8-10 Dec. 2014

Firstpage

1

Lastpage

7

Abstract

In this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory and reduces area, cost, energy consumption and hit latency. When compared with a Baseline Memory System, the PAMS consumes between 3 and 9 times and 1.13 and 2.66 times less program memory for static and dynamic data structures respectively. The benchmarking applications (having static and dynamic data structures) results show that PAMS consumes 20% less hardware resources, 32% less on chip power and achieves a maximum speedup of 52× and 2.9× for static and dynamic data structures respectively. The results show that the PAMS multi-core system transfers data structures up to 4.65× faster than the MicroBlaze baseline system.

Keywords

data structures; embedded systems; multiprocessing systems; storage management; MicroBlaze baseline system; PAMS multicore system; baseline memory system; dynamic data structure; embedded multicore memory system; embedded system; pattern aware memory system; static data structure; Data structures; Dynamic scheduling; Hardware; Memory management; Random access memory; Registers; Resource management;

fLanguage

English

Publisher

ieee

Conference_Titel

ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4799-5943-3

Type

conf

DOI

10.1109/ReConFig.2014.7032544

Filename

7032544