A Study of Failure Mechanism and Reliability Assessment for the Panel Level Package (PLP) Technology

In this study, a new packaging technology, chip-on-metal (COM) panel level package (PLP), is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. During the manufacturing process, the filler polymer material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler polymer and the chip surface, and the pitch of the chip side is fanned-out. In our previous research, it was shown that the thermo- mechanical behavior of the COM PLP is different from the convention wafer level package (WLP) because of the designed packaging structure. In this study, the reliability characteristic of the proposed PLP technology is investigated and discussed through finite element analysis (FEA). The macro-micro modeling methodology is applied to assist in the reliability assessment of the trace/pad junction. From the simulated results, the mean cycle to failure of the solder joints can be highly increased by the proposed packaging technology. However, the new failure mode may happen at the metallic redistribution layer. The reliability of the signal trace in the COM PLP can be improved by an experienced design of the trace layout. Thus, the proposed PLP technology will have a high potential for various applications in the near future.