Parameterised FPGA reconfigurations for efficient test set generation

This paper proposes the use of parameterised FPGA configurations for a new test set generation approach. The time-consuming problem of test set generation aims at finding the right input values to fully test an ASIC design. Since well-known methods for test set generation such as fault simulation techniques have become impractical to use due to their speed limitations, FPGAs have been used in order to facilitate fault injection techniques. However, the development of previous FPGA fault injection techniques demonstrate either area or time overhead. This paper proposes a post-synthesis fault injection method that combines fault emulation with the parameterised configuration technique. The new fault-injected design is mapped with different mapping solutions based on dynamic specialisation of the logic and routing infrastructure of the FPGA during runtime. The experimental results for the proposed technique indicate a significant reduction of the logic depth and an area reduction up to a factor 10 compared to conventional tools.