Test time reduction reusing multiple processors in a network-on-chip based architecture

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increase in the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the test access mechanism. Experimental results are based on ITC´02 benchmarks and on two open core processors, compliant with MIPS and SPARC instruction sets. The results show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins.