Design of Low Memory Usage Discrete Wavelet Transform on FPGA Using Novel Diagonal Scan

Discrete wavelet transform (DWT) is an efficient tool for multi-resolution decomposition of signal and image processing applications. During the compression of image using 2D-DWT two filters are used to evaluate a DWT, a highpass and a lowpass filter, with the filter coefficients derived from the wavelet basis function in each dimension. Among all DWTs, the Haar discrete wavelet transform (Haar DWT) is the simplest and orthogonal one. However, a traditional 2D DWT is applied by sequentially performing two 1D operations one along the rows and the other along the columns of a transformed row image. In other words, the column operation cannot be performed until the row operation is completed. There is decrease in performance due to the memory read and write operations involving intermediate result between row and column operations. Due to this reason, we propose the sequential data input to hierarchical algorithm for Haar DWT. With this technique, we can implement a 2D Haar DWT by data rearrangements, achieving the low memory required to implement being of O (N). The most important characteristic of this algorithm is that the computational process can be extended to image of any size taking the advantage of the block processing of image and data input using diagonal scan algorithm