A 87 pico-second CMOS variable delay line incorporating the parallel-resonator loads in K-band

This paper reports a variable delay line (VDL) with a tuning range of the group delay higher than 87 ps in K-band. The theoretical derivations show that the reflection load in the parallel form can make the reflection-type VDL achieve wider tuning range of the group delay than that of the reflection load in the series form. A practical prototype of the VDL is fabricated by using standard CMOS 0.13 μm 1P8M processes. The measured tuning range on the group delay confirms the predictions given by the design equations.