Title :
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding
Author :
Pastuszak, Grzegorz
Author_Institution :
Inst. of Radioelectron., Warsaw Univ. of Technol.
Abstract :
The number of clock cycles sacrificed to process binary symbols in hardware entropy coders may limit the performance of the whole H.264/AVC coder. This paper describes enhancements of the architecture based on the parallel symbol encoding. Five versions of the architecture are described to study the area/performance trade-off. The implementation results show that the parallel symbol encoding allows higher efficiency expressed as the area/performance ratio
Keywords :
arithmetic codes; binary codes; entropy codes; parallel architectures; video coding; H.264/AVC binary coder; arithmetic coding; binary symbol processing; hardware entropy coder; parallel symbol architecture; parallel symbol encoding; Arithmetic; Automatic voltage control; Clocks; Context modeling; Encoding; Entropy; Hardware; Probability; Throughput; Video compression;
Conference_Titel :
Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on
Conference_Location :
Bialystok
Print_ISBN :
0-7695-2554-7
DOI :
10.1109/PARELEC.2006.62
