Title :
Leakage-aware interconnect for on-chip network
Author :
Tsai, Yuh-Fang ; Narayaynan, Vijaykrishnan ; Xie, Yuan ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and the interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.
Keywords :
buffer circuits; driver circuits; integrated circuit interconnections; leakage currents; low-power electronics; multiprocessor interconnection networks; system-on-chip; NoC; active leakage savings; crossbars; delay penalty; leakage-aware interconnects; multiprocessors on chip; on-chip network; output drivers; power constrained systems; staggered threshold voltage buffers; standby leakage savings; systems-on-chip; Delay effects; Digital-to-frequency converters; Driver circuits; Integrated circuit interconnections; Network-on-a-chip; Output feedback; Power system interconnection; System-on-a-chip; Threshold voltage; Wires;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.195
