Device properties in 90 nm and beyond and implications on circuit design

Author

Diaz, C.H. ; Fung, K.H. ; Cheng, S.M. ; Cheng, K.L. ; Wang, S.W. ; Huang, H.T. ; Leung, Y.K. ; Tsai, M.H. ; Wu, C.C. ; Lin, C.C. ; Mi-Chang Chang ; Tang, D.

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

To reconcile scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization, gate dielectric scaling, strain-Si enhancement and I/O support.

Keywords

CMOS integrated circuits; capacitance; carrier lifetime; circuit optimisation; integrated circuit design; leakage currents; nanotechnology; nitridation; system-on-chip; I/O support; circuit design; flexible CMOS technologies; gate dielectric scaling; hot carrier lifetime; industry evolution requirements; leakage currents; leakage scaling; nitridation processes; parasitic capacitance scaling; performance-leakage power optimization; power supply scaling; scaling-driven fundamental material limitations; strain-Si enhancement; systems on chip; Appropriate technology; CMOS technology; Circuit synthesis; Dielectric materials; Electricity supply industry; Frequency; Leakage current; Power generation; Power supplies; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269162

Filename

1269162