Symmetric multiprocessing on programmable chips made easy

Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. However, it is a challenge to implement symmetric multiprocessor on a programmable chip (SMPoPC) systems using such processors. This paper presents an implementation of a tightly coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.