Title :
Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs
Author :
Takagi, S. ; Mizuno, T. ; Tezuka, T. ; Sugiyama, N. ; Numata, T. ; Usuda, K. ; Moriyama, Y. ; Nakaharai, S. ; Koga, J. ; Tanabe, A. ; Hirashita, N. ; Maeda, T.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; elemental semiconductors; semiconductor materials; silicon; silicon-on-insulator; 100 nm; MOSFET; Si-SiO/sub 2/; SiGe; carrier transport; channel engineering; channel structure design; strained-SOI CMOS technology; strained-SiGe-on-insulator; CMOS technology; Capacitive sensors; Charge carrier processes; Electron mobility; Fabrication; Germanium silicon alloys; MOS devices; MOSFETs; Silicon germanium; Thermal conductivity;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269165
