Substrate-strained silicon technology: process integration [CMOS technology]

Author

Wang, H.C.-H. ; Wang, Y.-P. ; Chen, S.-J. ; Ge, C.-H. ; Ting, S.M. ; Kung, J.-Y. ; Hwang, R.-L. ; Chiu, H.-K. ; Sheu, L.C. ; Tsai, P.-Y. ; Yao, L.-G. ; Chen, S.-C. ; Tao, H.-J. ; Yeo, Y.-C. ; Lee, W.-C. ; Hu, C.

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in I/sub on/-I/sub off/ characteristics without correction for self-heating effects is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased the off state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit manufacture; leakage currents; oscillators; silicon; 1.2 V; 6.5 ps; 60 nm; Si CMOS technology process integration; Si-SiGe; manufacturability; off state leakage; ring oscillator speed; self-heating effect; strained Si/SiGe heterostructure; substrate-strained silicon technology; CMOS technology; Germanium silicon alloys; Implants; Manufacturing industries; Manufacturing processes; Ring oscillators; Semiconductor device manufacture; Silicon germanium; Strain control; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269166

Filename

1269166