Dual mode logic based adder for energy efficient, high performance CMOS structures

Adders are the logic circuits designed to perform these arithmetic operations at a high speed. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. An approach that locates the design´s critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumption reduction. The proposed approach is analyzed on a 32 bit carry select adder. Simulations, carried out in a standard 180nm process technology with VDD =1.8V.