A new statistical model to extract the stress induced oxide trap number and the probability density distribution of the gate current produced by a single trap

Author

Driussi, F. ; Widdershoven, F. ; Esseni, D. ; van Duuren, M.J.

Author_Institution

DIEGM, Udine Univ., Italy

fYear

2003

fDate

8-10 Dec. 2003

Abstract

This work presents a new model to describe the statistical properties of SILC in non-volatile memory (NVM) arrays and a procedure to extract the average number of oxide traps and the probability density of the gate leakage current induced by a single trap directly from the measured histogram of SILC. The model and the extraction procedure have been validated on SILC distributions with known parameters, generated by Monte Carlo simulations, and applied to measurements performed on FLASH memory arrays. The sensitivity of the extracted parameters on the measurement resolution is discussed in detail.

Keywords

Monte Carlo methods; electron traps; flash memories; hole traps; integrated circuit measurement; integrated circuit modelling; leakage currents; random-access storage; FLASH memory arrays; Monte Carlo simulations; NVM; SILC distributions; gate leakage current probability density distribution; measurement resolution; nonvolatile memory arrays; single trap leakage; statistical model; stress induced leakage current; stress induced oxide trap number; Convolution; DC generators; Data mining; Histograms; Integrated circuit noise; Leakage current; Nonvolatile memory; Performance evaluation; Probability; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269199

Filename

1269199