Application of a multi-processor SoC platform to high-speed packet forwarding

Author

Paulin, Pierre G. ; Pilkington, Chuck ; Bensoudane, Essaid ; Langevin, Michel ; Lyonnard, Damien

Author_Institution

Central R&D, STMicroelectron., Ottawa, Ont., Canada

Volume

3

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

58

Abstract

In this paper, we explore the requirements of emerging complex SoC´s and describe StepNP, an experimental flexible, multi-processor SoC platform targeted towards communications and networking applications. We present the results of mapping an internet protocol (IPv4) packet forwarding application, running at 2.5 Gb/s and 10 Gb/s. We demonstrate how the use of high-speed hardware-assisted messaging and dynamic task allocation in the StepNP platform allows us to achieve very high processor utilization rates (up to 97%) in spite of the presence of high network-on-chip and memory access latencies. The inter-processor communication overhead is kept very low, representing only 9% of instructions.

Keywords

IP networks; multi-threading; multiprocessing systems; reduced instruction set computing; system-on-chip; 10 Gbyte/s; 2.5 Gbyte/s; Internet protocol; StepNP platform; dynamic task allocation; high speed packet forwarding; interprocessor communication; memory access latencies; multiprocessor SoC platform; multithreading; network-on-chip; reduced instruction set computing; system-on-chip; Application specific processors; Costs; Digital signal processing; Hardware; Libraries; Manufacturing; Network topology; Network-on-a-chip; Productivity; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1269203

Filename

1269203