DocumentCode :
2587800
Title :
An efficient algorithm for finding double-vertex dominators in circuit graphs
Author :
Teslenko, Maxim ; Dubrova, Elena
Author_Institution :
R. Inst. of Technol., Kista, Sweden
fYear :
2005
fDate :
7-11 March 2005
Firstpage :
406
Abstract :
Graph dominators provide a general mechanism for identifying re-converging paths in circuits. This is useful in a number of CAD applications, including computation of signal probabilities for test generation, switching activities for power and noise analysis, statistical timing analysis, cut point selection in equivalence checking, etc. Single-vertex dominators are too rare in circuit graphs to handle re-converging paths in a practical way. The paper addresses the problem of finding double-vertex dominators, which occur more frequently. First, we introduce a data structure, called dominator chain, which allows the representation of all possible O(n2) double-vertex dominators of a given vertex in O(n) space, where n is the number of vertices of the circuit graph. Dominator chains can be efficiently manipulated, e.g., it takes constant time to look-up whether a given pair of vertices is a double-vertex dominator. Second, we present an efficient algorithm for finding double-vertex dominators. The experimental results show that the presented algorithm is an order of magnitude faster than existing algorithms for finding double-vertex dominators. Thus, it is suitable for running in an incremental manner during logic synthesis.
Keywords :
circuit CAD; circuit analysis computing; graph theory; probability; CAD applications; circuit graphs; cut point selection; dominator chain data structure; double-vertex dominators; equivalence checking; graph dominators; noise analysis; power analysis; reconverging paths; signal probabilities; single-vertex dominators; statistical timing analysis; switching activities; test generation; Circuit noise; Circuit testing; Computer applications; Data structures; Noise generators; Power generation; Probability; Signal analysis; Signal generators; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2288-2
Type :
conf
DOI :
10.1109/DATE.2005.53
Filename :
1395594
Link To Document :
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