Title :
SAT-based complete don´t-care computation for network optimization
Author :
Mishchenko, Alan ; Brayton, Robert K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The paper describes an improved approach to Boolean network optimization using internal don´t-cares. The improvements concern the type of don´t-cares computed, their scope, and the computation method. Instead of the traditionally used compatible observability don´t-cares (CODCs), we introduce and justify the use of complete don´t-cares (CDC). To ensure the robustness of the don´t-care computation for very large industrial networks, an optional windowing scheme is implemented that computes substantial subsets of the CDCs in reasonable time. Finally, we give a SAT-based don´t-care computation algorithm that is more efficient than BDD-based algorithms. Experimental results confirm that these improvements work well in practice. Complete don´t-cares allow for a reduction in the number of literals compared to the CODCs. Windowing guarantees robustness, even for very large benchmarks on which previous methods could not be applied. SAT reduces the runtime and enhances robustness, making don´t-cares affordable for a variety of other Boolean methods applied to the network.
Keywords :
circuit optimisation; computability; logic circuits; logic design; BDD-based algorithms; Boolean network optimization; compatible observability don´t-cares; complete don´t-care computation; internal don´t-cares; logic synthesis; satisfiability; windowing scheme; Boolean functions; Computer industry; Computer networks; Data structures; Logic; Network synthesis; Observability; Optimization methods; Robustness; Runtime;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.264