The design of a high speed ASIC unit for the hash function SHA-256 (384, 512)

Author

Dadda, L. ; Macchetti, Marco ; Owen, Jeff

Author_Institution

ALaRI-USI, Lugano, Switzerland

Volume

3

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

70

Abstract

After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.

Keywords

adders; application specific integrated circuits; arrays; cryptography; high-speed integrated circuits; NIST; application specific integrated circuit; full adder arrays; hardware synthesis; hash function SHA-256; high speed ASIC design; national institute of standards and technology; Adders; Algorithm design and analysis; Application specific integrated circuits; Circuit synthesis; Delay; Hardware; Microelectronics; NIST; Partitioning algorithms; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1269207

Filename

1269207