Exploring energy/performance tradeoffs in shared memory MPSoCs: snoop-based cache coherence vs. software solutions

Shared memory is a common interprocessor communication paradigm for single-chip multi-processor platforms. Snoop-based cache coherence is a very successful technique that provides a clean shared-memory programming abstraction in general-purpose chip multiprocessors, but there is no consensus on its usage in resource-constrained multiprocessor systems on chips (MPSoC) for embedded applications. This work aims at providing a comparative energy and performance analysis of cache coherence support schemes in MPSoC. Thanks to the use of a complete multiprocessor simulation platform, which relies on accurate technology-homogeneous power models, we were able to explore different cache-coherent shared-memory communication schemes for a number of cache configurations and workloads.