Title :
A simple switched-capacitor algorithmic digital-to-analog converter using sample/hold and divider
Author :
Matsumoto, Hiroki
Author_Institution :
Dept. of Electr. Syst. Eng., Univ. of Miyazaki, Miyazaki, Japan
Abstract :
A novel switched-capacitor algorithmic digital-to-analog converter (D/A) is described. It is formed of one sample/hold and divider. Since no integrator is used, error caused by open loop gain of operational amplifier can easily be compensated. Required components are only two operational amplifiers, three unit capacitors and nine analog switches. Accuracy estimation shows that 12 bit resolution is possible on capacitor mismatch of 0.075%.
Keywords :
digital-analogue conversion; sample and hold circuits; switched capacitor networks; accuracy estimation; analog switches; capacitor mismatch; open loop gain; operational amplifier; sample-hold-divider circuit; switched-capacitor algorithmic digital-to-analog converter; unit capacitors; word length 12 bit; Accuracy; Capacitance; Capacitors; Clocks; Equations; Mathematical model; Operational amplifiers; D/A converter; divider; sample/hold; switched-capacitor;
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
DOI :
10.1109/APCCAS.2014.7032715
