DocumentCode :
258906
Title :
Live demonstration: A low-power high-level synthesis system
Author :
Hua-Hsin Yeh ; Chun-Hua Cheng ; Shih-Hsu Huang
Author_Institution :
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
fYear :
2014
fDate :
17-20 Nov. 2014
Firstpage :
165
Lastpage :
166
Abstract :
In this live demonstration, we present a low-power high-level synthesis system that performs the simultaneous application of operation scheduling and power management. The optimization goal is to maximize the power saving under both the timing constraints and the resource constraints. Moreover, we also develop a graphical user interface for the high-level synthesis system. Therefore, it is very easy for the user of the high-level synthesis system to perform the design space exploration (i.e., the trade-off between timing and power).
Keywords :
graphical user interfaces; high level synthesis; design space exploration; graphical user interface; low-power high-level synthesis system; operation scheduling; power management; power saving; resource constraints; timing constraints; Circuits and systems; Computers; Conferences; Graphical user interfaces; Optimization; Space exploration; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
Type :
conf
DOI :
10.1109/APCCAS.2014.7032743
Filename :
7032743
Link To Document :
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