Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Author

Haoming Zhang ; Dajiang Zhou ; Goto, Satoshi

Author_Institution

Grad. Sch. of Inf., Production & Syst. LSI, Waseda Univ., Kitakyushu, Japan

fYear

2014

fDate

17-20 Nov. 2014

Firstpage

169

Lastpage

170

Abstract

A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display module in different FPGA board and try to use two off-chip memory of the two boards, in order to provide more memory bandwidth.

Keywords

decoding; display instrumentation; field programmable gate arrays; high definition television; microprocessor chips; video coding; Altera Stratix III DE3 FPGA boards; FPGA-based 3840×2160 UHDTV H.264 video decoding; FPGA-based 3840×2160 UHDTV H.264 video displaying system; HSTC cable; decoder module; display module; memory bandwidth; off-chip memory; ultra-high definition TV H.264 video decoding; video processing system; Bandwidth; Decoding; Engines; Field programmable gate arrays; Hardware; Random access memory; Streaming media; FPGA; H.264; UHDTV; Video Decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on

Conference_Location

Ishigaki

Type

conf

DOI

10.1109/APCCAS.2014.7032745

Filename

7032745