• DocumentCode
    2589426
  • Title

    Multithreaded extension to multicluster VLIW processors for embedded applications

  • Author

    Barretta, Domenico ; Fornaciari, William ; Sami, Mariagiovanna ; Bagni, Daniele

  • Author_Institution
    Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
  • fYear
    2005
  • fDate
    7-11 March 2005
  • Firstpage
    748
  • Abstract
    Instruction level parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors.
  • Keywords
    embedded systems; multi-threading; parallel architectures; performance evaluation; ILP; embedded applications; instruction level parallelism; multicluster VLIW processors; multithreaded extension; performance; retargetable architecture; thread level parallelism; Computer architecture; Counting circuits; Dynamic scheduling; Parallel architectures; Parallel processing; Processor scheduling; Registers; Switches; VLIW; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2005. Proceedings
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-2288-2
  • Type

    conf

  • DOI
    10.1109/DATE.2005.219
  • Filename
    1395667
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2589426