DocumentCode :
258945
Title :
IC implementation of spike-timing-dependent synaptic plasticity model using low capacitance value
Author :
Yamashita, Daichi ; Saeki, Katsutoshi ; Sekine, Yoshifumi
Author_Institution :
Graduated Sch. of Sci. & Technol., Nihon Univ., Funabashi, Japan
fYear :
2014
fDate :
17-20 Nov. 2014
Firstpage :
221
Lastpage :
224
Abstract :
A number of recent studies on neural networks have been conducted with the purpose of applying engineering to the brain. An artificial neural networks (ANNs) were created that focus on how learning is achieved. In this paper, we focus on spike-timing-dependent synaptic plasticity (STDP) and construct an STDP model using semiconductors. We propose a new STDP model using a low capacitance value with CMOS technology, and show that the proposed integrated circuit has similar characteristics to biological neural networks.
Keywords :
CMOS integrated circuits; brain models; learning (artificial intelligence); neural nets; neurophysiology; ANN; CMOS technology; IC implementation; STDP model; artificial neural networks; biological neural networks; brain; integrated circuit; low capacitance value; semiconductors; spike-timing-dependent synaptic plasticity model; Biological neural networks; Biological system modeling; Brain modeling; Capacitance; Educational institutions; Integrated circuit modeling; Semiconductor device modeling; CMOS; artificial neural network nonlinear electronics circuit; integrated circuit; spike timing plasticity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location :
Ishigaki
Type :
conf
DOI :
10.1109/APCCAS.2014.7032759
Filename :
7032759
Link To Document :
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