A novel glitch reduction circuitry for binary-weighted DAC

Author

Fang-Ting Chou ; Chia-Min Chen ; Zong-Yi Chen ; Chung-Chih Hung

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

17-20 Nov. 2014

Firstpage

240

Lastpage

243

Abstract

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm² core area, and dissipates 19mW from a single 1.8V power supply.

Keywords

CMOS integrated circuits; buffer circuits; delay circuits; digital-analogue conversion; integrated circuit design; low-power electronics; DAC; SFDR; binary-weighted current-steering digital-to-analog converter; glitch reduction circuitry; low-power design; power 19 mW; size 0.18 mum; spurious free dynamic range; standard CMOS technology; variable-delay buffer; voltage 1.8 V; word length 10 bit; CMOS integrated circuits; Clocks; Current measurement; Delays; Latches; Resistors; Binary-weighted; DAC; variable-delay buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on

Conference_Location

Ishigaki

Type

conf

DOI

10.1109/APCCAS.2014.7032764

Filename

7032764