Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM

Author

Lee, D.-H. ; Lee, B.-C. ; Jung, I.-S. ; Taek Jung Kim ; Yong-Hoon Son ; Sun-Ghil Lee ; Young-Pil Kim ; Siyoung Choi ; U-In Chung ; Joo-Tae Moon

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea

fYear

2003

fDate

8-10 Dec. 2003

Abstract

For the first time, a highly manufacturable fin-channel array transistor (FCAT) on a bulk Si substrate has been successfully integrated in a 512 M density DRAM with sub-70nm technology. The FCAT shows an excellent short channel behavior, such as extremely low subthreshold swing (SS) (/spl sim/75mV/dec) and DIBL (/spl sim/13mV/V), and a high cell transistor drive current with remarkably low subthreshold leakage current (/spl sim/0.2fA/cell).

Keywords

DRAM chips; field effect transistors; leakage currents; low-power electronics; 0.2 fA; 512 Mbit; 70 nm; DIBL; FinFET; cell transistor drive current; fin-channel-array transistor; high performance DRAM; low power DRAM; low subthreshold swing; manufacturable FCAT; short channel behavior; subthreshold leakage current; Doping; Filling; FinFETs; Oxidation; Process design; Random access memory; Substrates; Subthreshold current; Transistors; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269309

Filename

1269309