A unified approach for FSM synthesis on FPGA architectures

We address the problem of finite state machines (FSM) synthesis for the two most popular Field Programmable Gate Array (FPGA) architectures : Actel and Xilinx. We propose a unified approach that deals with state assignment, optimization and mapping problems and that takes the target architecture into account during all the phases of the synthesis. This approach is made possible by very fast FPGA mapping techniques based on multi-ROBDD representation (Shared, Reduced and Ordered Binary Decision Diagrams). A prototype has been developed for FSM synthesis on Xilinx X3090 and Actel ACT1 architectures. Given a FSM description in VHDL or KISS format, it directly generates a look-up table (LUT) network for Xilinx or a multiplexor-based (MB) network for Actel. The results are promising and have been obtained within reasonable computing time. Comparisons have been made with the traditional approach implemented by Sis