High-efficient queue-based spin locks for Network-on-Chip processors

As one of the mostly used synchronization schemes in parallel programming, spin lock is supported in most off-the-shelf multi-/many-core processors. However the classical spin lock synchronization may lead to contention of acquiring the only lock and starvation of some threads busy waiting to be served. Thus queue-based spin lock has been put forwarded to eliminate both contention and unfairness issues of conventional schemes. Whereas applying queue-based spin lock synchronization in NoC processors introduces additional on-chip traffic to preserve serving sequence of participated cores. In this paper we propose a hardware solution of queue-based spin locks for NoC processors. A new instruction is designed to perform atomic read-after-write operations within single instruction, and a synchronization controller is used to handle global synchronization requests efficiently. Experimental results prove that our proposal outperforms former solutions and can save more than half time in some cases with marginal hardware overhead.