A high-throughput interpolator for fractional motion estimation in high efficient video coding (HEVC) systems

This paper presents design and implementation of a high throughput interpolator for the fractional motion estimation in HEVC systems. Novel data reusing scheme and highly parallel architecture are proposed such that timing efficiency and thus processing throughput of the system are enhanced. The detailed circuit architecture and timing analysis for the proposed interpolator will be given. Moreover, the proposed design is implemented based on FPGA platform as well as synthesized through the cell-based flow using TSMC 90nm process. The synthesized results show that, compared to the prior arts, the presented interpolator can achieve a 2.4x improvement in terms of generated fractional pixels per cycle. Moreover, when targeting 60 frame-per-seconds with Ultra High Definition resolution, the proposed design requires much lower operating frequency.