The Design and Implementation of Configurable High-Speed IP over AOS Gateway

Author

Feng Liu ; Hong Yan ; Huafeng Liu

Author_Institution

Sch. of Electron. & Inf. Eng., Beihang Univ., Beijing, China

fYear

2014

fDate

26-27 July 2014

Firstpage

82

Lastpage

86

Abstract

A system implementation framework is presented for configurable high-speed IP over AOS gateway in this paper. Pipeline operation and asynchronous FIFOs are adopted to achieve rate matching and data synchronization between different clock domains. The format of configuration packet of IP over AOS gateway and finite state machine description of protocol are given. The simulation results show that the gateway successfully implements IP over AOS protocol conversion and achieves over 1Gbps data transmission rate on Xilinx V5SX95T chip at 100MHz.

Keywords

IP networks; finite state machines; protocols; synchronisation; AOS gateway; AOS protocol conversion; Xilinx V5SX95T chip; advanced orbiting system protocol; asynchronous FIFO; clock domains; configurable high-speed IP; configuration packet format; data synchronization; finite state machine description; frequency 100 MHz; pipeline operation; rate matching; system implementation framework; Encapsulation; Field programmable gate arrays; IP networks; Logic gates; Protocols; Simulation; Synchronization; CCSDS; FPGA; Gateway; High-Speed; IP over AOS;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Applications and Communications (SCAC), 2014 IEEE Symposium on

Conference_Location

Weihai

Type

conf

DOI

10.1109/SCAC.2014.24

Filename

6913172