Title :
Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors
Author :
Boselli, G. ; Rodriguez, J. ; Duvvury, C. ; Reddy, V. ; Chidambaram, P.R. ; Hornung, B.
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A new phenomenon, reported in this paper for the first time, produces a dramatic reduction of the nMOS and pMOS triggering voltage (V/sub Tl/) under ESD conditions for an ultra-scaled 90 nm CMOS technology used in high performance applications. This V/sub Tl/ reduction is caused by the merging of pocket implants in short gate length transistors. This has a serious impact on the ESD sensitivity of output drivers, placing restrictions on the design of effective protection devices and burn-in voltage during product screening.
Keywords :
CMOS integrated circuits; MOSFET; doping profiles; electrostatic discharge; integrated circuit design; integrated circuit reliability; ion implantation; nanoelectronics; protection; 90 nm; CMOS transistors; ESD conditions; ESD design; ESD sensitivity; burn-in voltage; nMOS triggering voltage; output drivers; pMOS triggering voltage; pocket implant merging; product screening; protection device design; short gate length transistors; technology scaling effects; ultra-scaled CMOS technology; Bipolar transistors; Breakdown voltage; CMOS technology; Circuits; Electrostatic discharge; MOS devices; MOSFETs; Protection; Silicon; Space technology;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269332
