Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices

Supply voltage scaling greatly reduces the power consumption of circuits and is typically used in applications with loose speed constraints but tight power budgets. However, without digital standard cell libraries characterized at low voltages, integration of this technique is difficult in the semi-custom design flow. Thus, digital circuits are synthesized at the nominal voltage and their operating frequency is estimated at low voltages. However, this existing approach does not guarantee the timing of circuits containing standard cells with multiple threshold voltages whose delays scale differently as the supply voltage decreases. Slow high V_th non-critical paths are at risk of becoming critical paths at lower voltages that can cause timing errors. A new framework for timing analysis and removal of violating paths is then proposed for dual-V_th circuits. The framework is integrated in a 65nm CMOS digital flow and is verified using an 8-bit microcontroller core as the input design. The method successfully eliminated violating paths but the 35%-61% delay margin of the standard cell libraries contributed to the delay estimation errors.