Title :
Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation
Author :
Hazucha, P. ; Karnik, T. ; Maiz, J. ; Walstra, S. ; Bloechel, B. ; Tschanz, J. ; Dermer, G. ; Hareland, S. ; Armstrong, P. ; Borkar, S.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.
Keywords :
CMOS integrated circuits; SRAM chips; error statistics; integrated circuit design; integrated circuit measurement; integrated circuit reliability; neutron effects; 0.13 micron; 0.18 micron; 90 nm to 0.25 micron; CMOS process; CMOS technology; SER area dependency; SER linear scaling; SER voltage dependency; SRAM scaling trends; diode area; neutron SER; neutron soft error rate measurements; Area measurement; CMOS process; CMOS technology; Circuit testing; Error analysis; Neutrons; Particle beams; Printed circuits; Random access memory; Sea measurements;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269336
