Design and performance of a highly pipelined bus for shared memory multiprocessor

In a bus based shared memory multiprocessor system in which processors and memory modules are interconnected through system bus, time delay due to bus interference and memory contention degrades system performance. In order to reduce such delay, an optimal bus protocol and its hardware are necessary. In this study, a highly pipelined bus which splits a bus transaction into a request stage and a response stage is presented and analyzed. For the study, a software simulator was developed. Simulation results show that the proposed bus significantly (up to 27%) decreases the bus utilization as compared with a standard bus. The utilizations of resources and the degree of memory contention under different parameters also are shown