Title :
Statistical modeling of pipeline delay and design of pipeline under process variation to enhance yield in sub-100nm technologies
Author :
Datta, Animesh ; Bhunia, Swarup ; Mukhopadhyay, Saibal ; Banerjee, Nilanjan ; Roy, Kaushik
Author_Institution :
Dept. of ECE, Purdue Univ., West Lafayette, IN, USA
Abstract :
Operating frequency of a pipelined circuit is determined by the of the slowest pipeline stage. However, under statistical delay variation in sub-100 nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline. A statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield. Optimization results show that, proper imbalance among the stage delays in a pipeline improves design yield by 9% for the same area and performance (and area reduction by about 8.4% under a yield constraint) over a balanced design.
Keywords :
circuit optimisation; delays; integrated circuit design; integrated circuit modelling; integrated circuit yield; logic design; parameter estimation; pipeline processing; statistical analysis; analytical models; area reduction; balanced design; delay distributions; logic depth; nanometer technology regime; pipeline delay; pipeline design; pipeline stage delay; pipeline yield estimation; pipelined circuit operating frequency; pipelined design; process variation; process yield; stage delays imbalance; statistical delay variation; statistical modeling; statistical optimal design methodology; target delay; yield constraint; Analytical models; Circuits; Constraint optimization; Delay estimation; Design optimization; Frequency; Logic; Pipelines; Statistical analysis; Yield estimation;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.278