MAIN: Multiprocessor Architecture for Image Compression

Author

Laloya, Eduardo J. ; Navarro, Jesús

Author_Institution

Dept. de Ingenieria Electr. e Inf., Zaragoza Univ., Spain

fYear

1994

fDate

5-8 Sep 1994

Firstpage

210

Lastpage

215

Abstract

This paper presents a DSP-based parallel implementation intended for image compression. The basic processing module is built around the Texas Instruments TMS 320C25 digital signal processor (DSP). In this system the DSPs work in a parallel mode upon a divided image. Currently, the system is intended to perform compression of 256×256 8-bit images and can be easily adapted to work upon greater image sizes. Its modular design makes it expandable and allows to obtain real-time compression operation. The use of programmable DSPs permits the improvement and the partial/total change of the compression algorithm. Separate low-pass and high-pass image coding is used in the compression process. Compression ratio is dynamically adaptable and allows us to select the quality of the reconstructed images

Keywords

data compression; digital signal processing chips; image coding; multiprocessing systems; parallel algorithms; parallel architectures; real-time systems; DSP-based parallel implementation; MAIN; Multiprocessor Architecture for Image Compression; Texas Instruments TMS 320C25 digital signal processor; compression ratio; high-pass image coding; image compression; low-pass image coding; modular design; processing module; programmable DSPs; real-time compression operation; reconstructed images; Compression algorithms; Computer architecture; Digital signal processing; Discrete cosine transforms; Filtering; Image coding; Image reconstruction; Instruments; Low pass filters; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference.

Conference_Location

Liverpool

Print_ISBN

0-8186-6430-4

Type

conf

DOI

10.1109/EURMIC.1994.390389

Filename

390389