Device design considerations for ultra-thin SOI MOSFETs

Author

Doris, B. ; Ieong, M. ; Zhu, T. ; Zhang, Y. ; Steen, M. ; Natzle, W. ; Callegari, S. ; Narayanan, V. ; Cai, J. ; Ku, S.H. ; Jamison, P. ; Li, Yuhua ; Ren, Z. ; Ku, V. ; Boyd, T. ; Kanarsky, T. ; D´Emic, Chris ; Newport, M. ; Dobuzinsky, D. ; Deshpande, S.

Author_Institution

Microelectron. Div., IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA

fYear

2003

fDate

8-10 Dec. 2003

Abstract

The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO/sub 2/ gate dielectrics having appropriate threshold voltages are presented for the first time.

Keywords

MOSFET; elemental semiconductors; hafnium compounds; silicon; silicon-on-insulator; tungsten; 8 nm; HfO/sub 2/ gate dielectric; REX process scheme; Si-W-HfO/sub 2/; UTSOI; channel thickness; external resistance minimization; gate-length scaling; high temperature mobility; pFET; planar single gate nFET; raised extension process flow; tungsten gates; ultra-thin SOI MOSFET; Capacitance; Dielectric devices; Jamming; MOSFETs; Process design; Rapid thermal processing; Silicon; Temperature measurement; Threshold voltage; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269360

Filename

1269360