Title :
A new hardware cache coherence scheme
Author :
Cheng, José ; Finger, Ulrich ; Donnell, Ciaran O´
Author_Institution :
Dept. Inf., Ecole Nat. Superieure des Telecommun., Paris, France
Abstract :
Most existing directory-based protocols generate more coherence traffic and induce longer synchronization latency than required by the memory consistency model. A new cache coherence scheme is proposed for the entry consistency model. Locks are associated with shared data regions. Version numbers are associated with each block in the cache. The version number is compared with that of the latest writer on each access and stale data is updated from there or directly from memory. Using the scheme, protocol overhead traffic can be reduced by up to a factor of two. A lockup-free cache is assumed
Keywords :
cache storage; distributed processing; memory protocols; synchronisation; coherence traffic; directory-based protocols; entry consistency model; hardware cache coherence scheme; lockup-free cache; memory consistency model; protocol overhead traffic; shared data regions; synchronization latency; Access protocols; Coherence; Delay; Fingers; Hardware; Pipeline processing; Prefetching; Traffic control;
Conference_Titel :
EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference.
Conference_Location :
Liverpool
Print_ISBN :
0-8186-6430-4
DOI :
10.1109/EURMIC.1994.390399
