Title :
Atomic-layer-deposited ultrathin Si-nitride gate dielectrics - a better choice for sub-tunneling gate dielectrics
Author :
Nakajima, A. ; Ishii, H. ; Kitade, T. ; Yokoyama, S.
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Higashi-Hiroshima, Japan
Abstract :
The suitability of atomic-layer-deposited (ALD) Si nitride to meet the crying need for gate dielectrics with an EOT in the territory of 1 nm, has been investigated through an extensive and comparative study with conventional SiO/sub 2/ gate dielectrics. ALD Si nitride showed excellent reliability characteristics in all standard evaluations of MOS capacitors. Though the inversion layer mobility was slightly smaller for n-MOSFETs with an ALD Si nitride than for a SiO/sub 2/ gate dielectric, post-stress mobility degradation was much less for the ALD samples than for SiO/sub 2/ samples. The lower interface and bulk trap generation rates consistently explain the soft breakdown (SBD) free phenomena and the reduced mobility degradation for the ALD Si-nitride dielectrics. Therefore, the ALD Si-nitride dielectrics would be a better choice for sub-tunneling gate dielectrics.
Keywords :
MOS capacitors; MOSFET; atomic layer deposition; carrier mobility; dielectric thin films; interface states; silicon compounds; 1 nm; ALD; EOT; MOS capacitors; Si-SiN; Si-SiO/sub 2/; atomic-layer-deposited gate dielectrics; bulk trap generation; interface trap generation; inversion layer mobility; n-MOSFET; post-stress mobility degradation; soft breakdown free phenomena; sub-tunneling gate dielectrics; ultrathin gate dielectrics; Annealing; Boron; Breakdown voltage; Degradation; Dielectric breakdown; Dielectric devices; Leakage current; MOS capacitors; MOSFET circuits; Temperature;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269366
