DocumentCode
2590724
Title
Performance driven decoupling capacitor allocation considering data and clock interactions
Author
Chandy, Ajith ; Chen, Tom
Author_Institution
Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
fYear
2005
fDate
7-11 March 2005
Firstpage
984
Abstract
We propose a sensitivity-based method to allocate decoupling capacitors (decaps) incorporating leakage constraints and tighter data and clock interactions. The proposed approach attempts to allocate decaps not only based on the power grid integrity criteria, but also based on the impact of power grid noise on timing criticality and robustness. The resulting algorithm reduces the power grid noise to below a threshold and improves the performance or timing robustness of the circuit at the same time.
Keywords
CMOS integrated circuits; VLSI; capacitors; circuit simulation; clocks; integrated circuit layout; integrated circuit modelling; integrated circuit noise; power supply circuits; sensitivity; timing; CMOS scaling; circuit performance; data-clock interactions; decaps; leakage constraints; noise threshold; performance driven decoupling capacitor allocation; power grid integrity criteria; power grid noise; sensitivity-based method; timing criticality; timing robustness; Capacitance; Capacitors; Circuit noise; Clocks; Delay; Equations; Noise reduction; Noise robustness; Power grids; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2005. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2288-2
Type
conf
DOI
10.1109/DATE.2005.238
Filename
1395716
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