LVQ neural network SoC adaptable to different on-chip learning and recognition applications

The developed SoC in 180nm for the implementation of a Learning Vector Quantization (LVQ) neural network is based on a concept of hardware/software co-design for on-chip learning and recognition. Minimal Euclidean distance search, which is the most time consuming operation in the competition layer of the LVQ algorithm, is solved by a pipeline with parallel p-word input architecture. Very high flexibility is achieved because input number, neuron number in the competition layer, weight values, and output number are scalable for satisfying the requirements of different applications without changing the designed hardware. For example, in the case of a d-dimensional input vector, the classification can be completed in [d/p] +R clock cycles where R is the pipeline depth. An embedded 32-bit RISC CPU is mainly used for adjusting the values of the feature vectors which is not a time-critical operation in the LVQ algorithm.