Design of low power and improved tlatch comparator for SAR ADC

The design of low power and improved t_latch dynamic comparator for successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve low power performance, a modified dynamic comparator is proposed that use modified latch, utilizing NMOS transistor in the design. The t_latch of the proposed comparator improved by approximately 45% compared to conventional comparator. The proposed dynamic comparator is designed and simulated in a 0.18 μm CMOS process. Simulation results show that it only consumed 138 pW at 1.5 V power supply with clock frequency of 200 MHz.