New parallel MDC FFT processor with efiicient scheduling scheme

This paper presents a multi-path delay commutator (MDC) FFT processor for high-speed. The proposed FFT processor can achieve a high throughput by using a parallel datapath scheme and a multi-path delay commutator structure. The proposed processor can provide a low hardware complexity and an efficient scheduling scheme of complex multiplications. The proposed efficient scheduling scheme can reduce the number of complex multipliers from 8 to 6 without increasing delay and computation cycles. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The proposed eight-parallel FFT processor can provide a throughput rate of up to 2.7 Gsample/s at 338 MHz.