70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory

Author

Yong-Sik Yim ; Kwang-Shik Shin ; Sung-Hoi Hur ; Jae-Duk Lee ; Ihn-Gee Balk ; Hong-Soo Kim ; Soo-Jin Chai ; Eun-Young Choi ; Min-Cheol Park ; Dong-Seok Eun ; Sung-Bok Lee ; Hye-Jin Lim ; Sun-Pil Youn ; Sung-Hun Lee ; Tae-Jung Kim ; Han-Soo Kim ; Kyu-Charn

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea

fYear

2003

fDate

8-10 Dec. 2003

Abstract

A 4 Gb NAND flash memory with a 70 nm design rule is developed for mass storage applications. The cell size is 0.025 /spl mu/m/sup 2/, which is the smallest value ever reported. For the integration, an ArF lithography process along with resolution enhancing techniques was utilized, and poly-Si/W gate technology with an optimized re-oxidation process was implemented.

Keywords

elemental semiconductors; flash memories; oxidation; photolithography; silicon; tungsten; 4 Gbit; 70 nm; NAND flash technology; Si-W; flash memory cell size; lithography; mass storage; optimized re-oxidation process; poly-Si/W gate technology; resolution enhancing techniques; Digital audio players; Digital cameras; Fabrication; Flash memory; Lithography; Oxidation; Semiconductor device noise; Solid state circuits; Space technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269405

Filename

1269405