Title :
SOC testing methodology and practice
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
On a commercial digital still camera (DSC) controller chip, we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. The chip has been fabricated and tested successfully by our approach. Test results prove that short test integration cost, short test time, and small area overhead can be achieved. To support SOC testing, a memory BIST compiler and an SOC testing integration system have been developed.
Keywords :
built-in self test; integrated circuit testing; program compilers; scheduling; system-on-chip; SOC test integration platform; digital still camera controller chip; embedded memory built-in self-test; functional test timing; memory BIST compiler; scan IO sharing; test IO reduction; test scheduling; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Digital cameras; Logic testing; Random access memory; Read-write memory; System testing; Test pattern generators;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.273
