Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs

Author

Ohtake, H. ; Tagami, M. ; Arita, K. ; Hayashi, Y.

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

Misalignment-tolerant, Cu dual damascene interconnects (DDI) are successfully obtained in low-k SiOCH film (k=2.9) by a novel via-first multi-hard-mask (VF-MHM) process without via-poisoning of the photo-resist. In the VF-MHM, the etching sequence has higher misalignment margin between the vias and the upper lines in the Cu DDI as compared with a conventional trench-first one (TF-MHM). The VF-MHM process improves the fabrication yield and TDDB reliability of low-k/Cu-DDIs, and is a key scheme for sub-100 nm-node, ASIC fabrication.

Keywords

application specific integrated circuits; copper; dielectric thin films; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; masks; photoresists; silicon compounds; 100 nm; ASIC; Cu-SiOCH; DDI; TDDB reliability; VF-MHM etching sequence; dual damascene interconnects; fabrication yield improvement; low-k SiOCH film; misalignment-tolerant interconnects; multi-hard-mask process; photo-resist via-poisoning; via-first mask process; vias/upper lines misalignment margin; Application specific integrated circuits; Chemistry; Degradation; Etching; Fabrication; Lithography; National electric code; Protection; Semiconductor films; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269413

Filename

1269413