Delay estimation method for correlated net delay variations

This paper proposes an estimation method of the sub-paths with correlations. In recent years, the process variation may degrade the yield due to the timing error. The timing error is caused by the variation of the clock arrival times of flip-flops(FFs) and the path-delays between FFs from the expected value on the design. To recover this error, it is important to recognize the condition of the chip, especially the path-delay time. In this paper, the estimation of the variations with correlation is proposed. The proposed method utilizes that the variations with the correlation are described by the weight sum of independent random number using the coefficient from the correlations. We confirm the correctness of the proposed method compared with the Monte Carlo simulation.