Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Author

Wakabayashi, H. ; Yamagami, S. ; Ikezawa, N. ; Ogura, A. ; Narihiro, M. ; Arai, K. ; Ochiai, Y. ; Takeuchi, K. ; Yamamoto, T. ; Mogami, T.

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

Sub-10-nm planar-bulk-CMOS devices were clearly demonstrated by a lateral source/drain (S/D) junction control using the precisely-controlled gate-electrode, shallow source/drain extensions (SDE) and steep halo. Good cut-off characteristics were observed for n/pMOSFETs with the gate length of 5 nm at 0.4 V for the first time.

Keywords

MOSFET; annealing; electron beam lithography; etching; ion implantation; nanoelectronics; nitridation; Weibull plots; channel ion-implantation; cut-off characteristics; gate lithography; lateral junction control; planar-bulk-CMOS devices; plasma nitridation; precisely-controlled gate-electrode; shallow source/drain extensions; spike annealing; steep halo; Annealing; Dielectric thin films; Electrodes; Laboratories; Lithography; MOSFET circuits; Plasma temperature; Research and development; Resists; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269446

Filename

1269446

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2592150